Beschreibung
InhaltsangabeList of Figures. List of Tables. Preface. Acknowledgment. Chapter 1: introduction. 1.1 synthesis. 1.2 design approaches. 1.3 co-design. 1.4 structure and objective. Chapter 2: co-design methodology. 2.1 the co-design approach. 2.2 system specification. 2.3 hardware/software partitioning. 2.4 hardware synthesis. 2.5 software compilation. 2.6 interface synthesis. 2.7 system integration. 2.8 summary. Chapter 3: The co-design system. 3.1 development route. 3.2 target architecture. 3.3 performance results. 3.4 summary. Chapter 4: VHDL modeling of a co-design system. 4.1 modelling with VHDL. 4.2 the main system. 4.3 the microcontroller. 4.4 the dynamic memory: DRAM. 4.5 the coprocessor. 4.6 summary. Chapter 5: shared memory configuration. 5.1 case study. 5.2 timing characteristics. 5.3 memory accesses and interface mechanisms. 5.4 summary. Chapter 6: dual-port memory configuration. 6.1 general description. 6.2 the system architecture. 6.3 timing characteristics. 6.4 performance results. 6.5 summary. Chapter 7: cache memory configuration. 7.1 memory hierarchy design. 7.2 system organization. 7.3 timing characteristics. 7.4 performance results. 7.5 summary. Chapter 8: advanced topics and further research. 8.1 conclusions and achievements. 8.2 advanced topics and further research. Appendices. A: benchmark programs. B: top-level VHDL model of the co-design system. C: translating PALASMtm2 into VHDL. D: VHDL version of the case study. References. Index.
Produktsicherheitsverordnung
Hersteller:
Springer Verlag GmbH
juergen.hartmann@springer.com
Tiergartenstr. 17
DE 69121 Heidelberg
Autorenportrait
InhaltsangabeList of Figures. List of Tables. Preface. Acknowledgment. Chapter 1: introduction. 1.1 synthesis. 1.2 design approaches. 1.3 co-design. 1.4 structure and objective. Chapter 2: co-design methodology. 2.1 the co-design approach. 2.2 system specification. 2.3 hardware/software partitioning. 2.4 hardware synthesis. 2.5 software compilation. 2.6 interface synthesis. 2.7 system integration. 2.8 summary. Chapter 3: The co-design system. 3.1 development route. 3.2 target architecture. 3.3 performance results. 3.4 summary. Chapter 4: VHDL modeling of a co-design system. 4.1 modelling with VHDL. 4.2 the main system. 4.3 the microcontroller. 4.4 the dynamic memory: DRAM. 4.5 the coprocessor. 4.6 summary. Chapter 5: shared memory configuration. 5.1 case study. 5.2 timing characteristics. 5.3 memory accesses and interface mechanisms. 5.4 summary. Chapter 6: dual-port memory configuration. 6.1 general description. 6.2 the system architecture. 6.3 timing characteristics. 6.4 performance results. 6.5 summary. Chapter 7: cache memory configuration. 7.1 memory hierarchy design. 7.2 system organization. 7.3 timing characteristics. 7.4 performance results. 7.5 summary. Chapter 8: advanced topics and further research. 8.1 conclusions and achievements. 8.2 advanced topics and further research. Appendices. A: benchmark programs. B: top-level VHDL model of the co-design system. C: translating PALASMtm2 into VHDL. D: VHDL version of the case study. References. Index.
