This book describes techniques for how to verify and debug VLSI designs when bugs are found after the chips are fabricated and used in the field.  This is the first book to cover many aspects of post-silicon verification and debugging techniques that utilize high-level design information, such as design descriptions in C/C++. Using high-level analysis on the error traces generated by fabricated chips maximizes the efficiency of the verification and debugging techniques presented in this book. Experimental results are included for real applications of the techniques presented.

Hersteller:
Springer Verlag GmbH
juergen.hartmann@springer.com
Tiergartenstr. 17
DE 69121 Heidelberg

Introduction.- Hardware diagnosis, debug and correction for RTL/gate level designs.- Tracing techniques for design descriptions.- Extraction of high level stimulus from chip error trace.- Diagnosis based on transactions.- Hardware support for diagnosis.- Diagnosis for C-based designs.- Test pattern generation for C-based designs.- Patching (patchable) hardware.- Conclusions.